A hardware-algorithm co-design for Spiking Neural Networks achieves up to 69x energy efficiency gains using an SRAM-based Compute-in-Memory accelerator.
arXiv · March 16, 2026 · 2603.12739
Why it matters
It solves the 'O(N) state update' bottleneck in SNNs by replacing exponential decay with linear approximations that can be computed in-place in memory. For edge-AI practitioners, this offers a viable path toward ultra-low-power, event-driven inference on battery-constrained hardware.
From the abstract
Spiking Neural Networks (SNNs) have emerged as a biologically inspired alternative to conventional deep networks, offering event-driven and energy-efficient computation. However, their throughput remains constrained by the serial update of neuron membrane states. While many hardware accelerators and Compute-in-Memory (CIM) architectures efficiently parallelize the synaptic operation (W x I) achieving O(1) complexity for matrix-vector multiplication, the subsequent state update step still require